Design-Reuse5 年
Low Power Clock Multiplier PLL for 40nm TSMC ULP CMOS
The OT3135 is a flexible low power clock multiplier PLL function with a wide range of input and output frequencies, and is designed for TSMC 40nm, ULP CMOS processes.
Design-Reuse1 个月
SMIC Frequency multiplier IP Listing
The MXL-PLL-SYN is a high performance PLL based frequency synthesizer implemented using a digital CMOS technology. It is highly integrated and requires no external components. Differential circuit ...
Engineering360 News6 年
Digital Frequency Multiplier IC
Description: The 813N2532 device uses IDT 's fourth generation FemtoClock® NG technology for optimal high clock frequency and low phase noise performance, combined with a low power consumption and ...