How to display values of multi-dimensional array in VCS?
2005年1月20日 · mda reg vcs Hi, I wish to observe to changes of multi-dimension array (e.g. memory) in VCS . How to do that? I know Aldec and Modelsim can shows the value of those …
One problem on dumping fsdb file of verdi. - Forum for Electronics
2007年3月16日 · verdi -2001 -autoalias -f run.f -top system -ssf dump.fsdb -nologo The problem is that source files and fsdb can be imported but can not put any signal on nWave. When drag …
how to start with VCS, difference between VCS and DVE
2009年1月23日 · vcs debug_all Hi All, I am new to VCS; coming from a modelsim environment. Please let me know how to start with VCS. What is the difference between VCS and DVE. …
How to use VCS to watch the internal memory in my design?
2006年3月20日 · vcs dump memory contents what version of vcs u r using? vcs comes in 2 gui, virsim and dve. if you are using dve, there wont b any problem. follow the steps below: 1. vcs …
How to do coverage in vcs - Forum for Electronics
2010年10月4日 · Hi, I done my coverage in uvm_monitor. i am running the test in vcs tool. For coverage report I need simv.vdb file to run "urg" command. i am using the following command …
difference between debussy and verdi | Forum for Electronics
2010年4月6日 · mjvijai posted a nice list of module/feature (previous post) and that list provides a high-level feature names for what is new with Verdi. Each of those tools is integrated well into …
[SOLVED] - How To Merge Coverage in VCS? - Forum for Electronics
2017年6月7日 · Welcome to EDAboard.com Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, …
[SOLVED] - Verdi Mixed Design Help - Forum for Electronics
2013年8月30日 · I'm using the command 'verdi -f flist -vhdl' where flist is a list of files (both verilog and vhdl). When I have the -vhdl option it treats all files as vhdl, so the verilog ones give …
How to save these verdi configurations as ordinary user?
2016年11月22日 · Verdi is installed on the server. I am an ordinary user and only have the right to use it. I made some personalized settings on the verdi GUI(such as changing the default editor …
[SOLVED] - CLK stay 0 when VCS&Verdi simulation
2022年12月25日 · Hi, I'm tring to simulate a simple design adder, but when simulation, the CLK signal stay 0 so that no wave for me debug.